1. Field
Exemplary embodiments of the present invention relate to a memory device.
2. Description of the Related Art
Memory cells are the most basic unit for storing information and may each store one or more bits of data. Integration of memory devices has increased to the point where tens of millions of memory cells are included in a single memory device. But if even one memory cell has a defect, the memory device may not perform as required. However, discarding such memory devices would hurt product yield.
Several methods are being proposed to handle defective memory cells of memory devices. For example, a memory device may include extra cells (referred to as redundancy cells) in addition to memory cells. The memory device may be repaired using redundancy cells to replace the defective memory cells. This repair operation using redundancy cells is performed on each row/column. That is, the memory and redundancy cells are arranged in rows and columns for each cell block. When a defective memory cell occurs in a cell block, the row/column of memory cells that include the defective memory cell is substituted with a row/column of redundancy cells.
FIG. 1 is a diagram illustrating row repair operations for a memory device.
Referring to FIG. 1, the memory device may include a plurality of cell blocks 110 to 140, each including a plurality of word lines WL0 to WL511 and redundancy word lines RWL0 to RWL7, and address storage units 150 to 180 corresponding to the plurality of cell blocks 110 to 140. The address storage units 150 to 180 may include fuse sets FS0 to FS7 corresponding to the redundancy word lines of the cell blocks 110 to 140.
The address storage units 150 to 180 may store the addresses of the word lines to be replaced with the redundancy word lines in the cell block 110 to 140. For example, if the word line WL0 of the cell block 110 is to be replaced with the redundancy word line RWL0 of the cell block 110, the address of the word line WL0 of the cell block 110 may be stored in the fuse set FS0 of the address storage unit 150. When an active operation is performed, the memory device may activate the redundancy word line RWL0 of the cell block 110 instead of the word line WL0 of the cell block 110 using the address of the word line WL0 of the cell block 110 that has been stored in the fuse set FS0 of the address storage unit 150.
In the memory device of FIG. 1, the redundancy word lines of each cell block may replace only the word lines of the corresponding cell block in which they are included resulting in inefficiencies. For example, when 9 defective word lines are present in the cell block 110, all 9 defective word lines cannot be replaced because 8 redundancy word lines RWL0 to RWL7 are used in the cell block 110. Accordingly, the memory device is treated as defective product even if there are no defective word lines in the remaining cell blocks 120 to 140 and the remaining 24 redundancy word lines of the cell blocks 120 to 140 are not used.